University Defence Research Collaboration in Signal Processing

Optimal Memory Allocation and Power Minimization for FPGA-Based Image Processing

Publication:

IEEE Transactions on Circuits and Systems for Video Technology

Publication Author(s):

Paulo Garcia, Deepayan Bhowmik, Robert Stewart, Andrew Wallace and Greg Michaelson

Publication Date:

Jan 2019

Publication URL:

Work Package:

E_WP6

File Attachments:

Optimized Memory Allocation and Power Minimization for FPGA-Based Image Processing.pdf

The University Defence Research Collaboration (UDRC) in Signal Processing is delivered in partnership between Dstl (the Defence Science and Technology Laboratory), The University of Edinburgh, Heriot-Watt University, The Queen's University of Belfast and University of Strathclyde.