L_WP5: Low complexity algorithms and efficient implementation

To develop novel paradigms and implementation strategies for a range of complex signal processing algorithms operating in a networked environment. Links to WP1-WP4. (Relates to all themes) Low complexity algorithms will be targeted by both generic efficient approaches to common themes across the consortium, such as high-dimensional array data, and application-specific low-cost implementations through collaborative research and active engagement with all other WPs.

L_WP5.1 Data reduction and distributed processing

Lower dimensional representation of data can lead to significant cost reduction, including data-independent techniques such as frequency domain, sub-band or subspace-based processing and thinning of sensor data. This work will exploit a combination of data dependent and independent techniques to achieve a significant data reduction, and will demonstrate how this can be exploited in low-cost algorithms. Due to operating in a networked environment, the efficient organisation of algorithms across a distributed processing platform will be considered. This work will explore algorithms and applications from across all work packages. Areas of study include (i) Polynomial decompositions leading to sparse representations through data-dependent optimal transformations (e.g. Karhunen-Loeve transform (KLT)), for dimensionality reduction in beamformers (ii) Parallel implementations of linear algebra functions and distributed processing methods (e.g. systolic array design, IP core implementations, vector-codebook methods) to minimise the communications bandwidth between processing nodes and (iii) Statistical signal processing problems will be utilised to map algorithms to distributed processors, whereby constraints on the communication bandwidth between nodes need to be set (e.g. Bayesian belief network (BBN) structures).

L_WP5.2 Hardware realisations

Collaborating with Texas Instruments, Prism Tech, and Steepest Ascent, numerically efficient schemes are to be derived, with mappings onto suitable processing platforms to be investigated that demonstrate real-time algorithms in suitable test scenarios. Multi-core GPU-based platforms and programming environments such as CUDA are an enabling technology for massively parallel processing of data (facilitating real-time applications at low cost, but potentially high power consumption). In contrast, micro-controllers, DSP and FPGA based processing platforms are perfect candidates for low power, inexpensive sensor processing units. In collaboration with industrial partners, state-of-the-art Multicore DSP/FPGA embedded solutions are to emerge that are capable of matching the power-performance-price constraints posed by the range of specific problems arising within all work packages of the consortium.

Matlab Toolbox For Polynomial Matrix Decompositions

 

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